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authorYu Chien Peter Lin <peterlin@andestech.com>2024-02-22 16:39:41 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2024-03-12 07:13:14 -0700
commit95113bb705157f3518cec4ff0225a922507a0f8b (patch)
tree674951b431c629999d0fde450710ffc8f1d9cc12 /arch/riscv/boot
parentb88727d554f0fb826e0608192f59542497ba19c5 (diff)
riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240222083946.3977135-6-peterlin@andestech.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/boot')
-rw-r--r--arch/riscv/boot/dts/renesas/r9a07g043f.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a92cfcfc021b..099f3df75b42 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -39,7 +39,7 @@
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};