diff options
| author | Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2023-11-30 16:19:30 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-12-13 15:50:23 +0000 |
| commit | a29bb6564e1229da3c84c9123286ae19530c2190 (patch) | |
| tree | cde0453138dd5146dd1571c191ae9419b4b8c28e /arch/riscv/boot | |
| parent | 0a99b562e81554c4397ba6331e9b00501c88b15c (diff) | |
riscv: dts: starfive: Add JH7100 MMC nodes
Add device tree nodes for the Synopsis MMC controllers on the
StarFive JH7100 SoC.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 0cafac437746..c216aaecac53 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -178,6 +178,32 @@ riscv,ndev = <133>; }; + sdio0: mmc@10000000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SDIO0_AHB>, + <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>; + clock-names = "biu", "ciu"; + interrupts = <4>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + + sdio1: mmc@10010000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SDIO1_AHB>, + <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>; + clock-names = "biu", "ciu"; + interrupts = <5>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; |