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| author | Jisheng Zhang <jszhang@kernel.org> | 2023-06-18 00:15:28 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-06-17 19:04:08 +0100 |
| commit | 1203f584fe66522b0cf294424a35b4cfbc747d71 (patch) | |
| tree | 5f1d71b23637df7fd618dccfe1a0053ed4e79540 /arch/riscv/configs/defconfig | |
| parent | 5af4cb0c42c5ee084c40ae37f6ecce839b4f65bc (diff) | |
MAINTAINERS: add entry for T-HEAD RISC-V SoC
Currently, I would like to maintain the T-HEAD RISC-V SoC support.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/configs/defconfig')
0 files changed, 0 insertions, 0 deletions