diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2022-05-11 21:29:17 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-05-11 21:36:32 -0700 |
| commit | 100631b48ded73fcd8fdd7e17139cda92dfbfb79 (patch) | |
| tree | 1cdb9547e66c18b542591bcce0795bd3fd714522 /arch/riscv/include/asm/pgtable-bits.h | |
| parent | ffb0b0afbd7c2608b6608d693569f0e726efd26b (diff) | |
riscv: Fix accessing pfn bits in PTEs for non-32bit variants
On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10]
while on rv64 it is defined to use bits [53:10], leaving [63:54]
as reserved.
With upcoming optional extensions like svpbmt these previously
reserved bits will get used so simply right-shifting the PTE
to get the PFN won't be enough.
So introduce a _PAGE_PFN_MASK constant to mask the correct bits
for both rv32 and rv64 before shifting.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Link: https://lore.kernel.org/r/20220511192921.2223629-9-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/pgtable-bits.h')
| -rw-r--r-- | arch/riscv/include/asm/pgtable-bits.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index a6b0c89824c2..e571fa954afc 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -6,12 +6,6 @@ #ifndef _ASM_RISCV_PGTABLE_BITS_H #define _ASM_RISCV_PGTABLE_BITS_H -/* - * PTE format: - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * PFN reserved for SW D A G U X W R V - */ - #define _PAGE_ACCESSED_OFFSET 6 #define _PAGE_PRESENT (1 << 0) |