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authorAndrew Jones <ajones@ventanamicro.com>2023-01-29 01:28:51 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-01-31 23:29:40 -0800
commit1bc400ffb52b460eedc51ebd9b7753b7f2314878 (patch)
tree4fad74b3c3a2bf08fb38200b5b6f1fab34f97b7f /arch/riscv/kernel/cpufeature.c
parente0c267e03b0c77c9ac79ac08eada41ba8eb1b95f (diff)
riscv: module: Add ADD16 and SUB16 rela types
To prepare for 16-bit relocation types to be emitted in alternatives add support for ADD16 and SUB16. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230128172856.3814-9-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/kernel/cpufeature.c')
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