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authorAnup Patel <apatel@ventanamicro.com>2023-03-28 09:22:21 +0530
committerMarc Zyngier <maz@kernel.org>2023-04-08 11:26:24 +0100
commit18d2199d81054f44e6d2a51177cc80566f43bf23 (patch)
tree89e22a14d8ec806ae5e7818e436699193338e1df /arch/riscv/mm/cacheflush.c
parentfb0f3d281b7f81a11e210783940f3798c4744179 (diff)
RISC-V: Use IPIs for remote TLB flush when possible
If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote TLB flushes directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote TLB flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230328035223.1480939-6-apatel@ventanamicro.com
Diffstat (limited to 'arch/riscv/mm/cacheflush.c')
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