diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2023-10-09 10:37:49 +0100 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2023-10-13 21:19:25 +0200 |
| commit | c3f7c14856ebbeb8e9e19439b9f5ec66f88744b9 (patch) | |
| tree | 1d915ef7cd0488b0714edc80e464a1781fb11458 /arch/riscv | |
| parent | 61ebaa041f83677fa3ecd35e4c87e4332c16b4e9 (diff) | |
riscv: dts: allwinner: convert isa detection to new properties
Convert the D1 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 0856f18dc3cf..64c3c2e6cbe0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -25,6 +25,9 @@ mmu-type = "riscv,sv39"; operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; #cooling-cells = <2>; cpu0_intc: interrupt-controller { |