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authorAlexander Graf <agraf@suse.de>2012-10-31 13:36:18 +0100
committerAlexander Graf <agraf@suse.de>2012-10-31 13:36:18 +0100
commit0588000eac9ba4178cebade437da3b28e8fad48f (patch)
tree697e514a0a0193f17a54f372dd18c5cd3927e154 /arch/sh/include/uapi/asm/cachectl.h
parent8b5869ad85f703ffeb25e656eab826f6b85b984c (diff)
parent81c52c56e2b43589091ee29038bcf793d3f184ab (diff)
Merge commit 'origin/queue' into for-queue
Conflicts: arch/powerpc/include/asm/Kbuild arch/powerpc/include/uapi/asm/Kbuild
Diffstat (limited to 'arch/sh/include/uapi/asm/cachectl.h')
-rw-r--r--arch/sh/include/uapi/asm/cachectl.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/sh/include/uapi/asm/cachectl.h b/arch/sh/include/uapi/asm/cachectl.h
new file mode 100644
index 000000000000..6ffb4b7a212e
--- /dev/null
+++ b/arch/sh/include/uapi/asm/cachectl.h
@@ -0,0 +1,19 @@
+#ifndef _SH_CACHECTL_H
+#define _SH_CACHECTL_H
+
+/* Definitions for the cacheflush system call. */
+
+#define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */
+#define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */
+#define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */
+
+#define CACHEFLUSH_I 0x4
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE CACHEFLUSH_I /* flush instruction cache */
+#define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */
+#define BCACHE (ICACHE|DCACHE) /* flush both caches */
+
+#endif /* _SH_CACHECTL_H */