arch: remove tile port

The Tile architecture port was added by Chris Metcalf in 2010, and
maintained until early 2018 when he orphaned it due to his departure
from Mellanox, and nobody else stepped up to maintain it. The product
line is still around in the form of the BlueField SoC, but no longer
uses the Tile architecture.

There are also still products for sale with Tile-GX SoCs, notably the
Mikrotik CCR router family. The products all use old (linux-3.3) kernels
with lots of patches and won't be upgraded by their manufacturers. There
have been efforts to port both OpenWRT and Debian to these, but both
projects have stalled and are very unlikely to be continued in the future.

Given that we are reasonably sure that nobody is still using the port
with an upstream kernel any more, it seems better to remove it now while
the port is in a good shape than to let it bitrot for a few years first.

Cc: Chris Metcalf <chris.d.metcalf@gmail.com>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: http://www.mellanox.com/page/npu_multicore_overview
Link: https://jenkins.debian.net/view/rebootstrap/job/rebootstrap_tilegx_gcc7/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 0 insertions, 39 deletions

diff --git a/arch/tile/include/arch/mpipe_def.h b/arch/tile/include/arch/mpipe_def.h
deleted file mode 100644
index c3d30217fc66..000000000000
--- a/arch/tile/include/arch/mpipe_def.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_MPIPE_DEF_H__
-#define __ARCH_MPIPE_DEF_H__
-#define MPIPE_MMIO_ADDR__REGION_SHIFT 26
-#define MPIPE_MMIO_ADDR__REGION_VAL_CFG 0x0
-#define MPIPE_MMIO_ADDR__REGION_VAL_IDMA 0x4
-#define MPIPE_MMIO_ADDR__REGION_VAL_EDMA 0x5
-#define MPIPE_MMIO_ADDR__REGION_VAL_BSM 0x6
-#define MPIPE_BSM_REGION_VAL__VA_SHIFT 7
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_128 0x0
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_256 0x1
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512 0x2
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1024 0x3
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1664 0x4
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_4096 0x5
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_10368 0x6
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_16384 0x7
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_DFA 0x0
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_FIXED 0x1
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK 0x2
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY 0x3
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY_RAND 0x7
-#define MPIPE_LBL_NR_STATE__FIRST_WORD 0x2138
-#endif /* !defined(__ARCH_MPIPE_DEF_H__) */