diff options
| author | Peter Zijlstra <peterz@infradead.org> | 2022-05-20 15:38:43 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-09-07 21:54:04 +0200 |
| commit | dbf4e792beadafc684ef455453c613ff182c7723 (patch) | |
| tree | bdf73be176775efdfb9e8fac46f4e6fee983bc87 /arch/x86/events/core.c | |
| parent | 1acab2e01c9c5df00f2fddf3473014dea89dcb5f (diff) | |
perf/x86/p4: Remove perfctr_second_write quirk
Now that we have a x86_pmu::set_period() method, use it to remove the
perfctr_second_write quirk from the generic code.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220829101321.839502514@infradead.org
Diffstat (limited to 'arch/x86/events/core.c')
| -rw-r--r-- | arch/x86/events/core.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 05830bb77d40..b30b8bbcd1e2 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1356,7 +1356,7 @@ static void x86_pmu_enable(struct pmu *pmu) static_call(x86_pmu_enable_all)(added); } -static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); +DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); /* * Set the next IRQ period, based on the hwc->period_left value. @@ -1416,16 +1416,6 @@ int x86_perf_event_set_period(struct perf_event *event) if (is_counter_pair(hwc)) wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff); - /* - * Due to erratum on certan cpu we need - * a second write to be sure the register - * is updated properly - */ - if (x86_pmu.perfctr_second_write) { - wrmsrl(hwc->event_base, - (u64)(-left) & x86_pmu.cntval_mask); - } - perf_event_update_userpage(event); return ret; |