diff options
| author | Ingo Molnar <mingo@kernel.org> | 2016-04-28 10:35:17 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2016-04-28 10:35:17 +0200 |
| commit | 0b20e59cef927b030c2e626f40fc4965bacec847 (patch) | |
| tree | c090a7a4e2c20065eb5825debff1a724a7775b8a /arch/x86/events/intel/lbr.c | |
| parent | a8944c5bf86dc6c153a71f2a386738c0d3f5ff9c (diff) | |
| parent | cf3beb7c90a8efa16a06b26634cddddc92bb819c (diff) | |
Merge branch 'perf/urgent' into perf/core, to resolve conflict
Conflicts:
arch/x86/events/intel/pt.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/events/intel/lbr.c')
| -rw-r--r-- | arch/x86/events/intel/lbr.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 317e29e3869e..9e2b40cdb05f 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -64,7 +64,7 @@ static enum { #define LBR_PLM (LBR_KERNEL | LBR_USER) -#define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */ +#define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */ #define LBR_NOT_SUPP -1 /* LBR filter not supported */ #define LBR_IGN 0 /* ignored */ @@ -621,8 +621,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate * in suppress mode. So LBR_SELECT should be set to * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) + * But the 10th bit LBR_CALL_STACK does not operate + * in suppress mode. */ - reg->config = mask ^ x86_pmu.lbr_sel_mask; + reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) && (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) && |