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| author | Yu Zhang <yu.c.zhang@linux.intel.com> | 2017-08-24 20:27:56 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2017-08-24 18:09:17 +0200 |
| commit | fd8cb433734eeb870156a67f5d56b6564cd2ea94 (patch) | |
| tree | 6b82b558e2567346184d978d5d7d26cc157d3918 /arch/x86/kvm/kvm_cache_regs.h | |
| parent | 855feb6736403f398dd43764254c5f0522bfc130 (diff) | |
KVM: MMU: Expose the LA57 feature to VM.
This patch exposes 5 level page table feature to the VM.
At the same time, the canonical virtual address checking is
extended to support both 48-bits and 57-bits address width.
Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/kvm_cache_regs.h')
| -rw-r--r-- | arch/x86/kvm/kvm_cache_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 762cdf2595f9..0052317b2733 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -4,7 +4,7 @@ #define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS #define KVM_POSSIBLE_CR4_GUEST_BITS \ (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ - | X86_CR4_OSXMMEXCPT | X86_CR4_PGE) + | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_PGE) static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, enum kvm_reg reg) |