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authorJan H. Schönherr <jschoenh@amazon.de>2017-05-20 13:22:56 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2017-05-26 17:59:27 +0200
commite1d39b17e044e8ae819827810d87d809ba5f58c0 (patch)
tree6051dc367d678d3ecb89e770337cd9ab0a483838 /arch/x86/mm/testmmiotrace.c
parent5acc1ca4fb15f00bfa3d4046e35ca381bc25d580 (diff)
KVM: nVMX: Fix handling of lmsw instruction
The decision whether or not to exit from L2 to L1 on an lmsw instruction is based on bogus values: instead of using the information encoded within the exit qualification, it uses the data also used for the mov-to-cr instruction, which boils down to using whatever is in %eax at that point. Use the correct values instead. Without this fix, an L1 may not get notified when a 32-bit Linux L2 switches its secondary CPUs to protected mode; the L1 is only notified on the next modification of CR0. This short time window poses a problem, when there is some other reason to exit to L1 in between. Then, L2 will be resumed in real mode and chaos ensues. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/mm/testmmiotrace.c')
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