diff options
| author | Tero Kristo <t-kristo@ti.com> | 2014-07-02 11:47:42 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-07-15 14:09:06 -0600 |
| commit | 512d91cbd990c67df16d0a7b3ff5d35055ac6b39 (patch) | |
| tree | d9ebd1366f12859ab6184ffe8595c2649f186cff /arch | |
| parent | 5f84aeb6a194ed127d1beb61738577c15a60172b (diff) | |
ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features
OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses
clk_features data provided during boot. This avoids the need to use
cpu_is_X type checks runtime, and allows us to eventually move the
clock code under the clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/clkt_dpll.c | 25 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 17 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/clock.h | 1 |
3 files changed, 31 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 098e0893a6a6..49333d055f54 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -184,18 +184,19 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, */ static int _omap2_dpll_is_in_bypass(u32 v) { - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) + u8 mask, val; + + mask = ti_clk_features.dpll_bypass_vals; + + /* + * Each set bit in the mask corresponds to a bypass value equal + * to the bitshift. Go through each set-bit in the mask and + * compare against the given register value. + */ + while (mask) { + val = __ffs(mask); + mask ^= (1 << val); + if (v == val) return 1; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7efe66e3a029..e4384377d9f8 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -767,4 +767,21 @@ void __init ti_clk_init_features(void) ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; } + + /* Bypass value setup for DPLLs */ + if (cpu_is_omap24xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP2XXX_EN_DPLL_FRBYPASS); + } else if (cpu_is_omap34xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP3XXX_EN_DPLL_FRBYPASS); + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || + soc_is_omap54xx() || soc_is_dra7xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | + (1 << OMAP4XXX_EN_DPLL_MNBYPASS); + } } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 02aa2e3ac036..7b2b099c6a83 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -232,6 +232,7 @@ struct ti_clk_features { long fint_max; long fint_band1_max; long fint_band2_min; + u8 dpll_bypass_vals; }; extern struct ti_clk_features ti_clk_features; |