summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorVladimir Murzin <vladimir.murzin@arm.com>2017-06-12 13:35:52 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2017-06-12 15:47:29 +0100
commitd360a687d99577110c181e67ebfb9a1b6fed63a2 (patch)
treeac764253122a5234c0c229110f0b0b065a2d8f1d /arch
parentbbeedfda8eee0b17ea16e4e157c596095458676a (diff)
ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero
Cache support is optional feature in M-class cores, thus DminLine or IminLine of Cache Type Register is zero if caches are not implemented, but we check the whole CTR which has other features encoded there. Let's be more precise and check for DminLine and IminLine of CTR before we set cacheid. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/kernel/setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 32e1a9513dc7..4e80bf7420d4 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -315,7 +315,7 @@ static void __init cacheid_init(void)
if (arch >= CPU_ARCH_ARMv6) {
unsigned int cachetype = read_cpuid_cachetype();
- if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
+ if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
cacheid = 0;
} else if ((cachetype & (7 << 29)) == 4 << 29) {
/* ARMv7 register format */