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authorPaul Cercueil <paul@crapouillou.net>2018-05-20 16:31:17 +0000
committerStephen Boyd <sboyd@kernel.org>2018-06-01 23:21:39 -0700
commit6ee3d385c263248ce0ab2fcd679835082530445d (patch)
tree60e5ef12a0ee7715133b33ac72f9ef113f293ca1 /drivers/clk/ingenic
parenta6523b6fb8b54bd53b63c1ca171bed7d9dd3f68e (diff)
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
This is required, as we must not use the AHB1 bus before it is stable. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic')
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index 314f3143ca61..bf46a0df2004 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
[JZ4770_CLK_VPU] = {
"vpu", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H1CLK, },
- .gate = { CGU_REG_LCR, 30 },
+ .gate = { CGU_REG_LCR, 30, false, 150 },
},
[JZ4770_CLK_MMC0] = {
"mmc0", CGU_CLK_GATE,