diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-05-16 15:52:05 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-06-12 18:20:04 -0700 |
| commit | f235f6ae59e5060af6d924038348f94a6348ee8d (patch) | |
| tree | 1b285646e19ac33b18fb003f39f29aebadec6efc /drivers/clk/mediatek/clk-mt6779.c | |
| parent | 1775790eff4a8fa885db189c75f4ce98e7a6a1dc (diff) | |
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances,
share the same parent(s): in order to add parents selection in the
mtk-sd driver to achieve an accurate clock rate for all modes, remove
the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
will make sure that a clk_set_rate() call performed for a clock on
a secondary controller will not change the rate of a common parent,
which would result in an overclock or underclock of one of the
controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt6779.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt6779.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index ada927a61309..555e937e9430 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -687,16 +687,16 @@ static const struct mtk_mux top_muxes[] = { 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20), MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents, 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel", - msdc50_hclk_parents, 0x70, 0x74, 0x78, - 16, 2, 23, 0x004, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel", - msdc50_0_parents, 0x70, 0x74, 0x78, - 24, 3, 31, 0x004, 23), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel", + msdc50_hclk_parents, 0x70, 0x74, 0x78, + 16, 2, 23, 0x004, 22, 0), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel", + msdc50_0_parents, 0x70, 0x74, 0x78, + 24, 3, 31, 0x004, 23, 0), /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel", - msdc30_1_parents, 0x80, 0x84, 0x88, - 0, 3, 7, 0x004, 24), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel", + msdc30_1_parents, 0x80, 0x84, 0x88, + 0, 3, 7, 0x004, 24, 0), MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents, 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25), MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel", |