diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-05-16 15:52:05 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-06-12 18:20:04 -0700 |
| commit | f235f6ae59e5060af6d924038348f94a6348ee8d (patch) | |
| tree | 1b285646e19ac33b18fb003f39f29aebadec6efc /drivers/clk/mediatek/clk-mt8195-topckgen.c | |
| parent | 1775790eff4a8fa885db189c75f4ce98e7a6a1dc (diff) | |
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances,
share the same parent(s): in order to add parents selection in the
mtk-sd driver to achieve an accurate clock rate for all modes, remove
the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this
will make sure that a clk_set_rate() call performed for a clock on
a secondary controller will not change the rate of a common parent,
which would result in an overclock or underclock of one of the
controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8195-topckgen.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8195-topckgen.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 3acbd1c907ab..f4b3d8ba9ff4 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -930,15 +930,15 @@ static const struct mtk_mux top_mtk_muxes[] = { /* CLK_CFG_7 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis", spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk", - msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0", - msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1", - msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk", + msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0", + msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1", + msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0), /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2", - msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2", + msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0), MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir", intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1), MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus", |