diff options
| author | Georgi Djakov <georgi.djakov@linaro.org> | 2017-12-05 17:46:58 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2018-01-02 10:00:24 -0800 |
| commit | 0c6ab1b8f8940d4ddbfff7ddff080cbfb5f32b02 (patch) | |
| tree | 86310ba2d4e2a574951dffa428e33ac87972fa84 /drivers/clk/qcom/Makefile | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
clk: qcom: Add A53 PLL support
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.
This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Move to devm provider registration,
NUL terminate frequency table, made tristate/modular]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/Makefile')
| -rw-r--r-- | drivers/clk/qcom/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 26410d31446b..e767c60c24ec 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o |