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authorAmit Nischal <anischal@codeaurora.org>2018-04-09 14:11:44 +0530
committerStephen Boyd <sboyd@kernel.org>2018-04-16 21:12:12 -0700
commit44dbeebf14453f577dd1f15f5c4f55db47ac42a4 (patch)
tree0808a2cb33d8124a98df4b8cad0a53056320ab6e /drivers/clk/qcom/gdsc.h
parent687d7a0caa7736de53e3c5efdef6b5343d1470ac (diff)
clk: qcom: gdsc: Add support to reset AON and block reset logic
For some of the gdsc power domains, there could be need to reset the AON logic or assert/deassert the block control reset before removing the clamp_io. Add support for the same by introducing new flags SW_RESET and AON_RESET. Both SW reset and AON reset requires to be asserted for at least 1us before being de-asserted. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/gdsc.h')
-rw-r--r--drivers/clk/qcom/gdsc.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 39648348e5ec..9279278535cd 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -53,6 +53,8 @@ struct gdsc {
#define VOTABLE BIT(0)
#define CLAMP_IO BIT(1)
#define HW_CTRL BIT(2)
+#define SW_RESET BIT(3)
+#define AON_RESET BIT(4)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;