diff options
| author | Rajendra Nayak <rnayak@codeaurora.org> | 2016-09-29 14:05:46 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-02 14:52:58 -0700 |
| commit | 86c390dcd8cd1e248d60d5ce83575a02f029fda9 (patch) | |
| tree | e3ee782bb784d416ff99b98ad3d091480c6f779c /drivers/clk/qcom | |
| parent | 400d9fda39bc8e16412103796040aef484fe7f5d (diff) | |
clk: qcom: Add .is_enabled ops for clk-alpha-pll
This would be useful in subsequent patches when the .set_rate operation
would need to identify if the PLL is actually enabled
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Simplify return statement of is_enabled op]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index c6ddc04ea2f0..47a1da3739ce 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -199,6 +199,30 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) wait_for_pll_disable(pll); } +static int pll_is_enabled(struct clk_hw *hw, u32 mask) +{ + int ret; + u32 val, off; + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + + off = pll->offset; + ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + if (ret) + return ret; + + return !!(val & mask); +} + +static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) +{ + return pll_is_enabled(hw, PLL_ACTIVE_FLAG); +} + +static int clk_alpha_pll_is_enabled(struct clk_hw *hw) +{ + return pll_is_enabled(hw, PLL_LOCK_DET); +} + static int clk_alpha_pll_enable(struct clk_hw *hw) { int ret; @@ -408,6 +432,7 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, .recalc_rate = clk_alpha_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_alpha_pll_set_rate, @@ -417,6 +442,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); const struct clk_ops clk_alpha_pll_hwfsm_ops = { .enable = clk_alpha_pll_hwfsm_enable, .disable = clk_alpha_pll_hwfsm_disable, + .is_enabled = clk_alpha_pll_hwfsm_is_enabled, .recalc_rate = clk_alpha_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_alpha_pll_set_rate, |