diff options
| author | Paweł Jarosz <paweljarosz3691@gmail.com> | 2016-11-04 14:10:56 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-11-05 23:11:01 +0100 |
| commit | 82e56393a80b99cf8986616447d71cbcff90e9d1 (patch) | |
| tree | 3ff176f7fa80fb65d008cd8816709b7bedc89368 /drivers/clk/rockchip | |
| parent | 1dfbec3905548a0cbc820a62e1d8adee1c80bd41 (diff) | |
clk: rockchip: add 400MHz to rk3066 clock rates table
We need this to init PLL_CPLL to 400MHz at boot.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index a6d398f4b18f..062ef4960244 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = { RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4), |