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| author | Stephen Boyd <sboyd@kernel.org> | 2019-11-06 11:20:14 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-11-06 11:20:40 -0800 |
| commit | fac3810fb0b261716122b8337357358013920938 (patch) | |
| tree | 5362ef9ca10948a86d338be10015e4bb6b37ea5a /drivers/clk/samsung | |
| parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) | |
| parent | 50bf025b75902d326fdb8078be3d278e1b693576 (diff) | |
Merge tag 'clk-meson-v5.5-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk updates from Jerome Brunet:
- Add sm1 support in the Amlogic audio clock controller
* tag 'clk-meson-v5.5-1' of https://github.com/BayLibre/clk-meson:
clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
clk: meson: axg_audio: add sm1 support
clk: meson: axg-audio: provide clk top signal name
clk: meson: axg-audio: prepare sm1 addition
clk: meson: axg-audio: fix regmap last register
clk: meson: axg-audio: remove useless defines
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
dt-bindings: clk: axg-audio: add sm1 bindings
clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
clk: meson: g12a: fix cpu clock rate setting
clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
Diffstat (limited to 'drivers/clk/samsung')
0 files changed, 0 insertions, 0 deletions