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authorStephen Boyd <sboyd@kernel.org>2019-11-27 08:15:00 -0800
committerStephen Boyd <sboyd@kernel.org>2019-11-27 08:15:00 -0800
commitdabedfede32435ccb7cba4a8e527248d6aed6a39 (patch)
treefd88b415c17e615d26b3c7a9e5d94e2d511adc48 /drivers/clk/sprd
parent6df24d0c2f9d7991a0e50ac96512de59f420c9fa (diff)
parentfc59462c5ce60da119568fac325c92fc6b7c6175 (diff)
parenta31414e8c98dadbe0d31804804090e78ab1e0e9f (diff)
parent9320c7ddf968251073e8fcc7bbc376fd4c044f4c (diff)
parent9629dbdabd1983ef53f125336e1d62d77b1620f9 (diff)
parent46acbcb4849b2ca2e6e975e7c8130c1d61c8fd0c (diff)
Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and 'clk-pxa' into clk-next
- Make gpio gate clks propagate rate setting up to parent * clk-gpio-flags: clk: clk-gpio: propagate rate change to parent * clk-tegra: (23 commits) clk: tegra: Use match_string() helper to simplify the code clk: tegra: Fix build error without CONFIG_PM_SLEEP clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP clk: tegra: Optimize PLLX restore on Tegra20/30 clk: tegra: Add suspend and resume support on Tegra210 clk: tegra: Share clk and rst register defines with Tegra clock driver clk: tegra: Use fence_udelay() during PLLU init clk: tegra: clk-dfll: Add suspend and resume support clk: tegra: clk-super: Add restore-context support clk: tegra: clk-super: Fix to enable PLLP branches to CPU clk: tegra: periph: Add restore_context support clk: tegra: Support for OSC context save and restore clk: tegra: pll: Save and restore pll context clk: tegra: pllout: Save and restore pllout context clk: tegra: divider: Save and restore divider rate clk: tegra: Reimplement SOR clocks on Tegra210 clk: tegra: Reimplement SOR clock on Tegra124 clk: tegra: Rename sor0_lvds to sor0_out clk: tegra: Move SOR0 implementation to Tegra124 clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC ... * clk-rockchip: clk: rockchip: protect the pclk_usb_grf as critical on px30 clk: rockchip: add video-related niu clocks as critical on px30 clk: rockchip: move px30 critical clocks to correct clock controller clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc clk: rockchip: make clk_half_divider_ops static * clk-sprd: clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle() * clk-pxa: clk: pxa: fix one of the pxa RTC clocks