diff options
| author | Gabriel Fernandez <gabriel.fernandez@linaro.org> | 2015-10-07 11:08:57 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-10-08 23:52:58 -0700 |
| commit | 46a57afdd70c17cf15b2077c5ea611913f80f85f (patch) | |
| tree | cbf4f7eb306e7a7bbb7f42b1c30820b48c5b6710 /drivers/clk/st/clkgen.h | |
| parent | fb4738629b6c06c24ba0649ece20ecec978d8694 (diff) | |
drivers: clk: st: PLL rate change implementation for DVFS
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/st/clkgen.h')
| -rw-r--r-- | drivers/clk/st/clkgen.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/st/clkgen.h b/drivers/clk/st/clkgen.h index 35c863295268..f7ec2d9139d6 100644 --- a/drivers/clk/st/clkgen.h +++ b/drivers/clk/st/clkgen.h @@ -9,6 +9,8 @@ Copyright (C) 2014 STMicroelectronics #ifndef __CLKGEN_INFO_H #define __CLKGEN_INFO_H +extern spinlock_t clkgen_a9_lock; + struct clkgen_field { unsigned int offset; unsigned int mask; |