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authorTero Kristo <t-kristo@ti.com>2016-03-16 21:54:56 +0200
committerStephen Boyd <sboyd@codeaurora.org>2016-04-15 17:26:51 -0700
commit3db5ca27c80c15d20d0f1152dc34a5bcfa432ae6 (patch)
tree493e1efb87c4302d9aca7bd68c77f6b3f5b0a8a6 /drivers/clk/ti/clk-7xx.c
parentc5cc2a0bc930f1ae00b198aeb752acc3bdd4d5a7 (diff)
clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types. [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01 [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02 Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/ti/clk-7xx.c')
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