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authorStephen Boyd <sboyd@codeaurora.org>2013-07-18 16:21:26 -0700
committerJohn Stultz <john.stultz@linaro.org>2013-07-30 11:24:54 -0700
commit35702999b1f366ed80fc4bd94bd8ebc8a1c46954 (patch)
tree6fcf6640eca93812a986370ca05c6a4f79d00fdf /drivers/clocksource/tegra20_timer.c
parent2902b30e0bd78686e7d891519dbfe2e4e43825fd (diff)
clocksource: tegra: Switch to sched_clock_register()
The 32 bit sched_clock interface now supports 64 bits. Upgrade to the 64 bit function to allow us to remove the 32 bit registration interface. Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: John Stultz <john.stultz@linaro.org>
Diffstat (limited to 'drivers/clocksource/tegra20_timer.c')
-rw-r--r--drivers/clocksource/tegra20_timer.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 93961703b887..5cff61677b6c 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -98,7 +98,7 @@ static struct clock_event_device tegra_clockevent = {
.set_mode = tegra_timer_set_mode,
};
-static u32 notrace tegra_read_sched_clock(void)
+static u64 notrace tegra_read_sched_clock(void)
{
return timer_readl(TIMERUS_CNTR_1US);
}
@@ -200,7 +200,7 @@ static void __init tegra20_init_timer(struct device_node *np)
WARN(1, "Unknown clock rate");
}
- setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
+ sched_clock_register(tegra_read_sched_clock, 32, 1000000);
if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {