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authorDave Jiang <dave.jiang@intel.com>2024-10-28 14:46:17 -0700
committerDave Jiang <dave.jiang@intel.com>2024-10-28 14:46:17 -0700
commit86bcd81d66d63c549e98c9c502ccd3be01a52fe2 (patch)
tree2b52d5120714d9856439db66ad3a91ce413f7c25 /drivers/cxl/core/cdat.c
parent9474d586819940f00a98dd98015fe456f9b35452 (diff)
parentbdd7c35fc59f391de5a1d93ca7cbc715bf8c015c (diff)
Merge branch 'cxl/for-6.12/printf' into cxl-for-next
Add support for adding a printf specifier '$pra' to emit 'struct range' content.
Diffstat (limited to 'drivers/cxl/core/cdat.c')
-rw-r--r--drivers/cxl/core/cdat.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
index ef1621d40f05..438869df241a 100644
--- a/drivers/cxl/core/cdat.c
+++ b/drivers/cxl/core/cdat.c
@@ -247,8 +247,8 @@ static void update_perf_entry(struct device *dev, struct dsmas_entry *dent,
dpa_perf->dpa_range = dent->dpa_range;
dpa_perf->qos_class = dent->qos_class;
dev_dbg(dev,
- "DSMAS: dpa: %#llx qos: %d read_bw: %d write_bw %d read_lat: %d write_lat: %d\n",
- dent->dpa_range.start, dpa_perf->qos_class,
+ "DSMAS: dpa: %pra qos: %d read_bw: %d write_bw %d read_lat: %d write_lat: %d\n",
+ &dent->dpa_range, dpa_perf->qos_class,
dent->coord[ACCESS_COORDINATE_CPU].read_bandwidth,
dent->coord[ACCESS_COORDINATE_CPU].write_bandwidth,
dent->coord[ACCESS_COORDINATE_CPU].read_latency,
@@ -279,8 +279,8 @@ static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,
range_contains(&pmem_range, &dent->dpa_range))
update_perf_entry(dev, dent, &mds->pmem_perf);
else
- dev_dbg(dev, "no partition for dsmas dpa: %#llx\n",
- dent->dpa_range.start);
+ dev_dbg(dev, "no partition for dsmas dpa: %pra\n",
+ &dent->dpa_range);
}
}