summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2024-07-18 09:19:46 +1000
committerDave Airlie <airlied@redhat.com>2024-07-18 09:20:00 +1000
commit478a52707b0abe98aac7f8c53ccddb759be66b06 (patch)
treea2222f77ca078da421c60a8233e9bd3bc9d94b50 /drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
parentc58c39163a7e2c4c8885c57e4e74931c7b482e53 (diff)
parent1cff1010bef6f325d895db0306b59dc7232ed9b7 (diff)
Merge tag 'amd-drm-next-6.11-2024-07-12' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.11-2024-07-12: amdgpu: - RAS fixes - SMU fixes - GC 12 updates - SR-IOV fixes - IH 7 updates - DCC fixes - GC 11.5 fixes - DP MST fixes - GFX 9.4.4 fixes - SMU 14 updates - Documentation updates - MAINTAINERS updates - PSR SU fix - Misc small fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240712171637.2581787-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
index 9d3a3c778504..2542bd7aa7c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
@@ -274,7 +274,7 @@ int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry,
struct ras_query_context *qctx)
{
- u64 event_id = qctx->event_id;
+ u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;
RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");
RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n",
@@ -543,7 +543,7 @@ static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)
amdgpu_mca_bank_set_init(&mca_set);
- qctx.event_id = 0ULL;
+ qctx.evid.event_id = RAS_EVENT_INVALID_ID;
ret = amdgpu_mca_smu_get_mca_set(adev, type, &mca_set, &qctx);
if (ret)
goto err_free_mca_set;