diff options
| author | Le Ma <le.ma@amd.com> | 2019-11-12 16:52:46 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-10 00:01:57 -0500 |
| commit | cdf545f35f8f031432106a163583d3540d253c45 (patch) | |
| tree | e66161a5dd940dcf3a3e74d617f28e06403bd540 /drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |
| parent | d39da7dab14042fb7c10ee5fdc888a9ad3da362f (diff) | |
drm/amdgpu: add gfx v9 block support for aldebaran
Add gfx initial support
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 300a07227597..b3ca5c3d8f2a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -122,6 +122,10 @@ MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); +MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); + #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 @@ -1650,6 +1654,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) else chip_name = "green_sardine"; break; + case CHIP_ALDEBARAN: + chip_name = "aldebaran"; + break; default: BUG(); } @@ -2170,6 +2177,16 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) gb_addr_config &= ~0xf3e777ff; gb_addr_config |= 0x22010042; break; + case CHIP_ALDEBARAN: + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); + gb_addr_config &= ~0xf3e777ff; + gb_addr_config |= 0x22014042; + break; default: BUG(); break; @@ -2260,6 +2277,7 @@ static int gfx_v9_0_sw_init(void *handle) case CHIP_RAVEN: case CHIP_ARCTURUS: case CHIP_RENOIR: + case CHIP_ALDEBARAN: adev->gfx.mec.num_mec = 2; break; default: @@ -4647,7 +4665,8 @@ static int gfx_v9_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->asic_type == CHIP_ARCTURUS) + if (adev->asic_type == CHIP_ARCTURUS || + adev->asic_type == CHIP_ALDEBARAN) adev->gfx.num_gfx_rings = 0; else adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; @@ -6935,6 +6954,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) case CHIP_RAVEN: case CHIP_ARCTURUS: case CHIP_RENOIR: + case CHIP_ALDEBARAN: adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; break; default: |