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| author | Yifan Zha <Yifan.Zha@amd.com> | 2023-03-29 17:18:47 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-04-11 18:03:35 -0400 |
| commit | 554836cc24411e4d3645db5392655f8d28d1d47a (patch) | |
| tree | 6112c94ed0f0597cd1e8aa284abbc397619ae648 /drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | |
| parent | a2a0bdf1989c38ca2fc356edd23a114172ee09a2 (diff) | |
drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued
[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive
[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver
v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Horace Chen <horace.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/ih_v6_0.c')
0 files changed, 0 insertions, 0 deletions