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authorDave Airlie <airlied@redhat.com>2017-09-29 10:08:01 +1000
committerAlex Deucher <alexander.deucher@amd.com>2017-09-29 12:24:38 -0400
commit35b31f7c6464480b10f3a54c9a35699e02f17ae8 (patch)
tree0d59273b84ccea004d59c6d28ca10932917e24dc /drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
parent6cdb91e28128595c1e2b7d0fa1ead30dc34ff15c (diff)
amdgpu/soc15: make the pcie index/data registers constant.
These don't seem to change at runtime, and the initialisers are constant data. This could be improved by not selecting the apu/non-apu path on each pcie read/write access. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 045988b18bc3..7723d7bccb96 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -216,7 +216,10 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
}
struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
+const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
+ .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
+ .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
+};
int nbio_v6_1_init(struct amdgpu_device *adev)
{
@@ -235,9 +238,6 @@ int nbio_v6_1_init(struct amdgpu_device *adev)
nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
- nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
- nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
-
return 0;
}