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authorJun Lei <Jun.Lei@amd.com>2019-01-15 10:46:46 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-03-05 15:09:32 -0500
commit0f1a6ad724cd5270c7c7d1bba98ac1222a0943b6 (patch)
tree3a36f3eaaaf08b5693b68f088d92f14f9b0153d1 /drivers/gpu/drm/amd/display/dc/calcs
parentc7b0f71237af7e4ceb7bf723cf96b87178c00e54 (diff)
drm/amd/display: PPLIB Hookup
[Why] Make dml and integration with pplib clearer. [How] Change the way the dml formula is initialized to make its values more clear. Restructure DC interface with pplib into rv_funcs. Cap clocks received from pplib. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs')
-rw-r--r--drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 12d1842079ae..2a807b9f77f7 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1391,7 +1391,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
{
- struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
+ struct pp_smu_funcs_rv *pp = &dc->res_pool->pp_smu->rv_funcs;
struct pp_smu_wm_range_sets ranges = {0};
int min_fclk_khz, min_dcfclk_khz, socclk_khz;
const int overdrive = 5000000; /* 5 GHz to cover Overdrive */