diff options
| author | Harry Wentland <harry.wentland@amd.com> | 2019-02-25 13:26:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:07 -0500 |
| commit | 97bda0322b8a91aa8d534763e709571b2334e585 (patch) | |
| tree | 9e572c249b54a91c58a771d5eeef5ffc51cfe587 /drivers/gpu/drm/amd/display/dc/core/dc.c | |
| parent | b4f199c7b00c87183f10c0a8f635f26ba2ede3eb (diff) | |
drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
| ^
v |
+--------+ +--------+
| DPP | | DWB |
+--------+ +--------+
|
v ^
+--------+ |
| MPC | |
+--------+ |
| |
v |
+-------+ +-------+ |
| OPP | <--> | DSC | |
+-------+ +-------+ |
| |
v |
+--------+ /
| OPTC | --------------
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
v2: rebase (Alex)
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 052d3c8c6b73..68eddcc0fbcc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -56,6 +56,10 @@ #include "dc_link_dp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#include "dsc.h" +#endif + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 #include "vm_helper.h" #endif @@ -1730,6 +1734,23 @@ static void commit_planes_do_stream_update(struct dc *dc, #endif } +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) + if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) { + if (stream_update->dsc_config->num_slices_h && + stream_update->dsc_config->num_slices_v) { + /* dsc enable */ + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true); + dp_set_dsc_enable(pipe_ctx, true); + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false); + } else { + /* dsc disable */ + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true); + dp_set_dsc_enable(pipe_ctx, false); + dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false); + } + + } +#endif /* Full fe update*/ if (update_type == UPDATE_TYPE_FAST) continue; |