diff options
| author | Qingqing Zhuo <Qingqing.Zhuo@amd.com> | 2023-07-28 17:55:30 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-09 16:48:51 -0400 |
| commit | 7966f319c66d9468623c6a6a017ecbc0dd79be75 (patch) | |
| tree | 362b3b39b0083075a106b16b58b4b495fbae38f9 /drivers/gpu/drm/amd/display/dc/core/dc_resource.c | |
| parent | 6e2c4941ce0cbe54a7bab8e18c5070e7dc5986f5 (diff) | |
drm/amd/display: Introduce DML2
DC is transitioning from DML to DML2, and this commit introduces all the
required changes for some of the already available ASICs and adds the
required code infra to support new ASICs under DML2. DML2 is also a
generated code that provides better mode verification and programming
models for software/hardware, and it enables a better way to create
validation tools. This version is more like a middle step to the
complete transition to the DML2 version.
Changes since V1:
- Alex: Fix typos
Changes since V2:
- Update DC includes
Changes since V3:
- Fix 32 bit compilation issues on x86
Changes since V4:
- Avoid compilation of DML2 on some not supported 32-bit architecture
- Update commit message
Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Co-developed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index aa7b5db83644..c1e2f0e10ab2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -41,6 +41,7 @@ #include "dpcd_defs.h" #include "link_enc_cfg.h" #include "link.h" +#include "clk_mgr.h" #include "virtual/virtual_link_hwss.h" #include "link/hwss/link_hwss_dio.h" #include "link/hwss/link_hwss_dpia.h" @@ -86,6 +87,8 @@ dc->ctx->logger #define DC_LOGGER_INIT(logger) +#include "dml2/dml2_wrapper.h" + #define UNABLE_TO_SPLIT -1 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) @@ -318,6 +321,10 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, res_pool->ref_clocks.xtalin_clock_inKhz; res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; + if ((res_pool->hubbub->funcs->get_dchub_ref_freq)) + res_pool->hubbub->funcs->get_dchub_ref_freq(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); } else ASSERT_CRITICAL(false); } @@ -4358,9 +4365,22 @@ void dc_resource_state_copy_construct( { int i, j; struct kref refcount = dst_ctx->refcount; +#ifdef CONFIG_DRM_AMD_DC_FP + struct dml2_context *dml2 = NULL; + + // Need to preserve allocated dml2 context + if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2) + dml2 = dst_ctx->bw_ctx.dml2; +#endif *dst_ctx = *src_ctx; +#ifdef CONFIG_DRM_AMD_DC_FP + // Preserve allocated dml2 context + if (src_ctx->clk_mgr->ctx->dc->debug.using_dml2) + dst_ctx->bw_ctx.dml2 = dml2; +#endif + for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; |