diff options
| author | Charlene Liu <charlene.liu@amd.com> | 2019-06-27 18:16:21 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:27:25 -0500 |
| commit | 925f566cb7aedbcf26005035cf894ec824e8ca2f (patch) | |
| tree | 06f5ac58c76e29af2bfce31f2adbf3787ae7bbda /drivers/gpu/drm/amd/display/dc/dc_types.h | |
| parent | 30db43b62c16cb0a0ff3eb89d9b25bf455859ef8 (diff) | |
drm/amd/display: add set and get clock for testing purposes
add dc_set_clock
add dc_get_clock
this is for testing and diagnostics to get/set DPPCLK and DISPCLK.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_types.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ce6d73d21cca..b273735b6a3e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -726,6 +726,19 @@ struct AsicStateEx { unsigned int phyClock; }; + +enum dc_clock_type { + DC_CLOCK_TYPE_DISPCLK = 0, + DC_CLOCK_TYPE_DPPCLK = 1, +}; + +struct dc_clock_config { + uint32_t max_clock_khz; + uint32_t min_clock_khz; + uint32_t bw_requirequired_clock_khz; + uint32_t current_clock_khz;/*current clock in use*/ +}; + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSC DPCD capabilities */ union dsc_slice_caps1 { |