diff options
| author | Tony Cheng <tony.cheng@amd.com> | 2017-02-28 21:30:32 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:17:51 -0400 |
| commit | d98e5cc2ddacb34e9cdf1c06dce2758198af0120 (patch) | |
| tree | 66a0ce231d31e37b4e2e1eaa2aede4f95a876bed /drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | |
| parent | 2d60ded1325e0b4407aaa5396d1b331ea58f4f85 (diff) | |
drm/amd/display: clean up and simply locking logic
always take update lock instead of using HW built in update
lock trigger with write to primary_addr_lo.
we will be a little more inefficient with the extra registers
write to lock, but this simplify code and make it always correct.
Will revisit locking optimization once update sequence mature
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 1e1d60af8306..89a8274e12ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -52,8 +52,7 @@ void dce_pipe_control_lock(struct core_dc *dc, uint32_t lock_val = lock ? 1 : 0; uint32_t dcp_grph, scl, blnd, update_lock_mode, val; struct dce_hwseq *hws = dc->hwseq; - if (control_mask & PIPE_LOCK_CONTROL_MPCC_ADDR) - return; + val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx], BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph, BLND_SCL_V_UPDATE_LOCK, &scl, |