diff options
author | Tony Cheng <tony.cheng@amd.com> | 2017-07-12 22:35:52 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:30 -0400 |
commit | 0a87425a37b4c1f06d75949ea39e60455a2b0a4f (patch) | |
tree | af34f92ecf058199aaaecb2874bc17aa6a0a9ed8 /drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | |
parent | 8c4abe0b07a12c402f009abed8217e6c2e33a300 (diff) |
drm/amd/display: move VGA to HWSS from TG
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 80ee1ac32fee..7feb1ca9b8c0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -170,7 +170,12 @@ SR(DIO_MEM_PWR_CTRL), \ SR(DCCG_GATE_DISABLE_CNTL), \ SR(DCCG_GATE_DISABLE_CNTL2), \ - SR(DCFCLK_CNTL) + SR(DCFCLK_CNTL),\ + SR(DCFCLK_CNTL), \ + SR(D1VGA_CONTROL), \ + SR(D2VGA_CONTROL), \ + SR(D3VGA_CONTROL), \ + SR(D4VGA_CONTROL) #endif #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -236,6 +241,10 @@ struct dce_hwseq_registers { uint32_t MPC_CRC_RESULT_GB; uint32_t MPC_CRC_RESULT_C; uint32_t MPC_CRC_RESULT_AR; + uint32_t D1VGA_CONTROL; + uint32_t D2VGA_CONTROL; + uint32_t D3VGA_CONTROL; + uint32_t D4VGA_CONTROL; #endif }; /* set field name */ |