diff options
| author | Harry Wentland <harry.wentland@amd.com> | 2017-01-23 11:49:24 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:11:28 -0400 |
| commit | f0e3db90a6fbee4acc921a4912a3e3460efb5cc0 (patch) | |
| tree | fb1b9350ae3ba693651e63b84f8b5a91c49cd617 /drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | |
| parent | adc9b14139de00b9fe016acc901a5fcf50145008 (diff) | |
drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 64fae91dd5eb..fa8699d3b9ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1243,7 +1243,7 @@ static bool construct( /************************************************* * Resource + asic cap harcoding * *************************************************/ - pool->base.underlay_pipe_index = -1; + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = pool->base.res_cap->num_timing_generator; dc->public.caps.max_downscale_ratio = 200; dc->public.caps.i2c_speed_in_khz = 100; |