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authorCharlene Liu <charlene.liu@amd.com>2019-06-05 15:21:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 14:18:08 -0500
commitc70b4016306a10b2c6e5d5da96a1f04a6248900f (patch)
tree80b4faadc649cca1bcbec76bb3d30cf574130b57 /drivers/gpu/drm/amd/display/dc/dce
parent08900ab73225584e4a260223a0848e2825e226fe (diff)
drm/amd/display: Split out common HUBP registers and code
There are shared regs and code across DCN generations. Pull them out into a shared common location. Also, expose some dcn20 init functions. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index cb0a037b1c4a..3a49f1ffb5dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -696,7 +696,8 @@ struct dce_hwseq_registers {
type D2VGA_MODE_ENABLE; \
type D3VGA_MODE_ENABLE; \
type D4VGA_MODE_ENABLE; \
- type AZALIA_AUDIO_DTO_MODULE;
+ type AZALIA_AUDIO_DTO_MODULE;\
+ type HPO_HDMISTREAMCLK_GATE_DIS;
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)