diff options
| author | Vitaly Prosyak <vitaly.prosyak@amd.com> | 2017-07-13 15:42:58 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:12 -0400 |
| commit | 4bd3ae5fb5156eb47b4d7f4f12d8467d9c4a8623 (patch) | |
| tree | 3822be3ce18d4cb1d333306d77b54baa53c346da /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | |
| parent | b02c3b055fe27cb37969c68cd81db767a16af43b (diff) | |
drm/amd/display: Move view port registers and programming to memory input.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 993643552aff..c1124e962d0e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -59,12 +59,6 @@ SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ SRI(DSCL_2TAP_CONTROL, DSCL, id), \ - SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ - SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ - SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ - SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ - SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ - SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ SRI(MPC_SIZE, DSCL, id), \ SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ @@ -144,18 +138,6 @@ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ - TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ - TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ - TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ - TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ - TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ @@ -257,18 +239,6 @@ type SCL_V_2TAP_SHARP_EN; \ type SCL_V_2TAP_SHARP_FACTOR; \ type SCL_COEF_RAM_SELECT; \ - type PRI_VIEWPORT_WIDTH; \ - type PRI_VIEWPORT_HEIGHT; \ - type PRI_VIEWPORT_X_START; \ - type PRI_VIEWPORT_Y_START; \ - type SEC_VIEWPORT_WIDTH; \ - type SEC_VIEWPORT_HEIGHT; \ - type SEC_VIEWPORT_X_START; \ - type SEC_VIEWPORT_Y_START; \ - type PRI_VIEWPORT_WIDTH_C; \ - type PRI_VIEWPORT_HEIGHT_C; \ - type PRI_VIEWPORT_X_START_C; \ - type PRI_VIEWPORT_Y_START_C; \ type DSCL_MODE; \ type RECOUT_START_X; \ type RECOUT_START_Y; \ @@ -355,12 +325,6 @@ struct dcn_dpp_registers { uint32_t SCL_COEF_RAM_TAP_SELECT; uint32_t SCL_COEF_RAM_TAP_DATA; uint32_t DSCL_2TAP_CONTROL; - uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; - uint32_t DCSURF_PRI_VIEWPORT_START; - uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; - uint32_t DCSURF_SEC_VIEWPORT_START; - uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; - uint32_t DCSURF_PRI_VIEWPORT_START_C; uint32_t MPC_SIZE; uint32_t SCL_HORZ_FILTER_SCALE_RATIO; uint32_t SCL_VERT_FILTER_SCALE_RATIO; |