diff options
author | Yue Hin Lau <Yuehin.Lau@amd.com> | 2017-07-23 12:13:37 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:34 -0400 |
commit | c8d7bd8bd0c08aa9115589d264e274ed7fdf4c2e (patch) | |
tree | 8aac0b00aa3308e5d4e210388ff62a1984521aa1 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | |
parent | e63825be738ea0bb975aee43b603ac5f0190d7a8 (diff) |
drm/amd/display: move RGAM programming from opp to dpp
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 499 |
1 files changed, 494 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 693060e79d21..34085c0818e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -71,7 +71,8 @@ SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \ SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ SRI(RECOUT_START, DSCL, id), \ - SRI(RECOUT_SIZE, DSCL, id) + SRI(RECOUT_SIZE, DSCL, id), \ + SRI(OBUF_CONTROL, DSCL, id) #define TF_REG_LIST_DCN10(id) \ TF_REG_LIST_DCN(id), \ @@ -93,7 +94,70 @@ SRI(CM_OCSC_C21_C22, CM, id), \ SRI(CM_OCSC_C23_C24, CM, id), \ SRI(CM_OCSC_C31_C32, CM, id), \ - SRI(CM_OCSC_C33_C34, CM, id) + SRI(CM_OCSC_C33_C34, CM, id), \ + SRI(CM_MEM_PWR_CTRL, CM, id), \ + SRI(CM_RGAM_LUT_DATA, CM, id), \ + SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ + SRI(CM_RGAM_LUT_INDEX, CM, id), \ + SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \ + SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_2_3, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_4_5, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_6_7, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_8_9, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_10_11, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_12_13, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_14_15, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_16_17, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_18_19, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_20_21, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_22_23, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_24_25, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_26_27, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_28_29, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_30_31, CM, id), \ + SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \ + SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \ + SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \ + SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \ + SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_2_3, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_4_5, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_6_7, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_8_9, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_10_11, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_12_13, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_14_15, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_16_17, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_18_19, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_20_21, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_22_23, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_24_25, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_26_27, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \ + SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ + SRI(CM_RGAM_CONTROL, CM, id) #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\ TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\ @@ -169,7 +233,8 @@ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ - TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh) + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ + TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh) #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\ TF_REG_LIST_SH_MASK_DCN(mask_sh),\ @@ -214,7 +279,186 @@ TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \ TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ - TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh) + TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ + TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \ + TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ + TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ + TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ + TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh) #define TF_REG_FIELD_LIST(type) \ @@ -333,7 +577,187 @@ type CM_OCSC_C31; \ type CM_OCSC_C32; \ type CM_OCSC_C33; \ - type CM_OCSC_C34 + type CM_OCSC_C34; \ + type RGAM_MEM_PWR_FORCE; \ + type CM_RGAM_LUT_DATA; \ + type CM_RGAM_LUT_WRITE_EN_MASK; \ + type CM_RGAM_LUT_WRITE_SEL; \ + type CM_RGAM_LUT_INDEX; \ + type CM_RGAM_RAMB_EXP_REGION_START_B; \ + type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ + type CM_RGAM_RAMB_EXP_REGION_START_G; \ + type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \ + type CM_RGAM_RAMB_EXP_REGION_START_R; \ + type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \ + type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \ + type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \ + type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \ + type CM_RGAM_RAMB_EXP_REGION_END_B; \ + type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \ + type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \ + type CM_RGAM_RAMB_EXP_REGION_END_G; \ + type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \ + type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \ + type CM_RGAM_RAMB_EXP_REGION_END_R; \ + type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \ + type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \ + type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \ + type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \ + type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION_START_B; \ + type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ + type CM_RGAM_RAMA_EXP_REGION_START_G; \ + type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ + type CM_RGAM_RAMA_EXP_REGION_START_R; \ + type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ + type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \ + type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \ + type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \ + type CM_RGAM_RAMA_EXP_REGION_END_B; \ + type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \ + type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \ + type CM_RGAM_RAMA_EXP_REGION_END_G; \ + type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \ + type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \ + type CM_RGAM_RAMA_EXP_REGION_END_R; \ + type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \ + type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \ + type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ + type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type CM_RGAM_LUT_MODE; \ + type OBUF_BYPASS; \ + type OBUF_H_2X_UPSCALE_EN struct dcn_dpp_shift { TF_REG_FIELD_LIST(uint8_t); @@ -397,6 +821,70 @@ struct dcn_dpp_registers { uint32_t CM_OCSC_C23_C24; uint32_t CM_OCSC_C31_C32; uint32_t CM_OCSC_C33_C34; + uint32_t CM_MEM_PWR_CTRL; + uint32_t CM_RGAM_LUT_DATA; + uint32_t CM_RGAM_LUT_WRITE_EN_MASK; + uint32_t CM_RGAM_LUT_INDEX; + uint32_t CM_RGAM_RAMB_START_CNTL_B; + uint32_t CM_RGAM_RAMB_START_CNTL_G; + uint32_t CM_RGAM_RAMB_START_CNTL_R; + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; + uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; + uint32_t CM_RGAM_RAMB_END_CNTL1_B; + uint32_t CM_RGAM_RAMB_END_CNTL2_B; + uint32_t CM_RGAM_RAMB_END_CNTL1_G; + uint32_t CM_RGAM_RAMB_END_CNTL2_G; + uint32_t CM_RGAM_RAMB_END_CNTL1_R; + uint32_t CM_RGAM_RAMB_END_CNTL2_R; + uint32_t CM_RGAM_RAMB_REGION_0_1; + uint32_t CM_RGAM_RAMB_REGION_2_3; + uint32_t CM_RGAM_RAMB_REGION_4_5; + uint32_t CM_RGAM_RAMB_REGION_6_7; + uint32_t CM_RGAM_RAMB_REGION_8_9; + uint32_t CM_RGAM_RAMB_REGION_10_11; + uint32_t CM_RGAM_RAMB_REGION_12_13; + uint32_t CM_RGAM_RAMB_REGION_14_15; + uint32_t CM_RGAM_RAMB_REGION_16_17; + uint32_t CM_RGAM_RAMB_REGION_18_19; + uint32_t CM_RGAM_RAMB_REGION_20_21; + uint32_t CM_RGAM_RAMB_REGION_22_23; + uint32_t CM_RGAM_RAMB_REGION_24_25; + uint32_t CM_RGAM_RAMB_REGION_26_27; + uint32_t CM_RGAM_RAMB_REGION_28_29; + uint32_t CM_RGAM_RAMB_REGION_30_31; + uint32_t CM_RGAM_RAMB_REGION_32_33; + uint32_t CM_RGAM_RAMA_START_CNTL_B; + uint32_t CM_RGAM_RAMA_START_CNTL_G; + uint32_t CM_RGAM_RAMA_START_CNTL_R; + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; + uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; + uint32_t CM_RGAM_RAMA_END_CNTL1_B; + uint32_t CM_RGAM_RAMA_END_CNTL2_B; + uint32_t CM_RGAM_RAMA_END_CNTL1_G; + uint32_t CM_RGAM_RAMA_END_CNTL2_G; + uint32_t CM_RGAM_RAMA_END_CNTL1_R; + uint32_t CM_RGAM_RAMA_END_CNTL2_R; + uint32_t CM_RGAM_RAMA_REGION_0_1; + uint32_t CM_RGAM_RAMA_REGION_2_3; + uint32_t CM_RGAM_RAMA_REGION_4_5; + uint32_t CM_RGAM_RAMA_REGION_6_7; + uint32_t CM_RGAM_RAMA_REGION_8_9; + uint32_t CM_RGAM_RAMA_REGION_10_11; + uint32_t CM_RGAM_RAMA_REGION_12_13; + uint32_t CM_RGAM_RAMA_REGION_14_15; + uint32_t CM_RGAM_RAMA_REGION_16_17; + uint32_t CM_RGAM_RAMA_REGION_18_19; + uint32_t CM_RGAM_RAMA_REGION_20_21; + uint32_t CM_RGAM_RAMA_REGION_22_23; + uint32_t CM_RGAM_RAMA_REGION_24_25; + uint32_t CM_RGAM_RAMA_REGION_26_27; + uint32_t CM_RGAM_RAMA_REGION_28_29; + uint32_t CM_RGAM_RAMA_REGION_30_31; + uint32_t CM_RGAM_RAMA_REGION_32_33; + uint32_t CM_RGAM_CONTROL; + uint32_t OBUF_CONTROL; }; struct dcn10_dpp { @@ -413,6 +901,7 @@ struct dcn10_dpp { int lb_pixel_depth_supported; int lb_memory_size; int lb_bits_per_entry; + bool is_write_to_ram_a_safe; }; bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, struct dc_context *ctx, |