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| author | Dillon Varone <Dillon.Varone@amd.com> | 2022-11-11 14:06:58 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-11-23 09:01:53 -0500 |
| commit | e667ee3b0c049bf0c69426879586a2572bb28d26 (patch) | |
| tree | e1247aed16850beba7d76e2eed7c5f995b26ead7 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | |
| parent | 2a5dd86a69ea5435f1a837bdb7fafcda609a7c91 (diff) | |
drm/amd/display: Use new num clk levels struct for max mclk index
[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.
[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c')
0 files changed, 0 insertions, 0 deletions