diff options
| author | Leo (Sunpeng) Li <sunpeng.li@amd.com> | 2017-05-16 16:07:30 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:07:19 -0400 |
| commit | 5aff86c1b3259f1443e0b35b74eb6dfd5b35791b (patch) | |
| tree | 1953f025f213dcee082fc283064aee7c8542ccec /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | |
| parent | 98489c026edc48d9c783f783cc82f2e8811e0ee4 (diff) | |
drm/amd/display: Implement input gamma LUT
1. Implemented dcn10_ipp_program_input_lut(), following the existing
interface.
2. Added missing registers as needed
3. Change to REG_GET for *ram_select() funcs.
4. Removed gamma table init from DiagsDM::make_surface() for resolving
CRC errors. Reason: Legacy LUT will be deprecated soon for Raven in
favor of degamma/regamma.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index a4ea4e774c72..511993519740 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -87,6 +87,8 @@ SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ SRI(CM_MEM_PWR_CTRL, CM, id), \ SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ + SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ + SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ SRI(CM_DGAM_LUT_INDEX, CM, id), \ SRI(CM_DGAM_LUT_DATA, CM, id), \ @@ -238,7 +240,13 @@ IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \ + IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \ IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \ + IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \ + IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \ + IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \ + IPP_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \ + IPP_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \ IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \ @@ -251,6 +259,9 @@ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \ IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ + IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ + IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ + IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \ IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ @@ -404,7 +415,16 @@ type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ type SHARED_MEM_PWR_DIS; \ + type CM_IGAM_LUT_FORMAT_R; \ + type CM_IGAM_LUT_FORMAT_G; \ + type CM_IGAM_LUT_FORMAT_B; \ type CM_IGAM_LUT_HOST_EN; \ + type CM_IGAM_LUT_RW_INDEX; \ + type CM_IGAM_LUT_RW_MODE; \ + type CM_IGAM_LUT_WRITE_EN_MASK; \ + type CM_IGAM_LUT_SEL; \ + type CM_IGAM_LUT_SEQ_COLOR; \ + type CM_IGAM_DGAM_CONFIG_STATUS; \ type CM_DGAM_LUT_WRITE_EN_MASK; \ type CM_DGAM_LUT_WRITE_SEL; \ type CM_DGAM_LUT_INDEX; \ @@ -507,6 +527,8 @@ struct dcn10_ipp_registers { uint32_t CM_DGAM_RAMA_REGION_14_15; uint32_t CM_MEM_PWR_CTRL; uint32_t CM_IGAM_LUT_RW_CONTROL; + uint32_t CM_IGAM_LUT_RW_INDEX; + uint32_t CM_IGAM_LUT_SEQ_COLOR; uint32_t CM_DGAM_LUT_WRITE_EN_MASK; uint32_t CM_DGAM_LUT_INDEX; uint32_t CM_DGAM_LUT_DATA; |