diff options
| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2017-12-20 17:17:40 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:17:33 -0500 |
| commit | f8e413bf3c478225177ff74510ecf6bcd6160d1b (patch) | |
| tree | 4fde875f4c3ce503e5ed0ef15f753f875b837bdf /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | |
| parent | 2e9d6a571cb7e5a9218e3f43f1c6de5649b4e373 (diff) | |
drm/amd/display: Move dpp reg access from hwss to dpp module.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index d7b5bd20352a..819b749c6e31 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -33,7 +33,6 @@ #define IPP_REG_LIST_DCN(id) \ SRI(FORMAT_CONTROL, CNVC_CFG, id), \ - SRI(DPP_CONTROL, DPP_TOP, id), \ SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ SRI(CURSOR0_COLOR0, CNVC_CUR, id), \ @@ -130,7 +129,6 @@ struct dcn10_ipp_mask { }; struct dcn10_ipp_registers { - uint32_t DPP_CONTROL; uint32_t CURSOR_SETTINS; uint32_t CURSOR_SETTINGS; uint32_t CNVC_SURFACE_PIXEL_FORMAT; |