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authorTony Cheng <tony.cheng@amd.com>2017-08-03 21:23:04 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 18:16:23 -0400
commit8a5d82451e297fc3864bb9ab0247b53c7ab8a022 (patch)
tree366adab8301fc08405c76300a9ef61bd25272010 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
parent5aa72db72ccc08c2d3d3e4b0a285bab932db5132 (diff)
drm/amd/display: use some sensible time out
40s time out is not sensible. also make all udelay poll happen more frequently since CPU is busy anyways Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 036f161ab1c1..52f2f2dd9a43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -72,7 +72,7 @@ static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id)
ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
REG_WAIT(MPCC_STATUS[id],
MPCC_IDLE, 1,
- 1000, 1000);
+ 1, 100000);
}
static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10)