diff options
| author | Qingqing Zhuo <qingqing.zhuo@amd.com> | 2019-07-23 12:24:24 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:56:34 -0500 |
| commit | 1ba0a5802fba04f2b0680ae12f478d9be93517d6 (patch) | |
| tree | 4b2e581462e5b3f0db7ce170da35337ed748c753 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | |
| parent | e40837afb9b011757e17e9f71d97853ca574bcff (diff) | |
drm/amd/display: Add enum for H-timing divider mode
Add h_timing_div_mode enum to better reflect possible register
values. Replace previously programmed values with enum
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index b631786a4a34..e5e5be63032b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -154,7 +154,7 @@ void optc1_program_timing( uint32_t h_sync_polarity, v_sync_polarity; uint32_t start_point = 0; uint32_t field_num = 0; - uint32_t h_div_2; + enum h_timing_div_mode h_div = H_TIMING_NO_DIV; struct optc *optc1 = DCN10TG_FROM_TG(optc); @@ -285,10 +285,11 @@ void optc1_program_timing( * of stereo handled in explicit call */ - h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); - REG_UPDATE(OTG_H_TIMING_CNTL, - OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->opp_count == 2); + if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) + h_div = H_TIMING_DIV_BY2; + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_BY2, h_div); } void optc1_set_vtg_params(struct timing_generator *optc, |