diff options
| author | Corbin McElhanney <corbin.mcelhanney@amd.com> | 2017-08-16 11:49:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:16:50 -0400 |
| commit | 214435ff1369a9d48c194c7a75d918130c53bab2 (patch) | |
| tree | 66433028ebd87d8dc8981f79870cbe3765dc1482 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | |
| parent | b05dee52efdcb6286a28be4dddeb450b58591c6d (diff) | |
drm/amd/display: Log OTG registers with dcn10 hw state
Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 747e8211e507..654889318fc1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -67,6 +67,7 @@ SRI(OTG_CLOCK_CONTROL, OTG, inst),\ SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ + SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ SRI(OPPBUF_CONTROL, OPPBUF, inst),\ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ SRI(CONTROL, VTG, inst),\ @@ -121,6 +122,7 @@ struct dcn_tg_registers { uint32_t OTG_CLOCK_CONTROL; uint32_t OPTC_INPUT_CLOCK_CONTROL; uint32_t OPTC_DATA_SOURCE_SELECT; + uint32_t OPTC_INPUT_GLOBAL_CONTROL; uint32_t OPPBUF_CONTROL; uint32_t OPPBUF_3D_PARAMETERS_0; uint32_t CONTROL; @@ -204,6 +206,7 @@ struct dcn_tg_registers { SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ @@ -310,6 +313,7 @@ struct dcn_tg_registers { type OPTC_INPUT_CLK_GATE_DIS;\ type OPTC_SRC_SEL;\ type OPTC_SEG0_SRC_SEL;\ + type OPTC_UNDERFLOW_OCCURRED_STATUS;\ type OPPBUF_ACTIVE_WIDTH;\ type OPPBUF_3D_VACT_SPACE1_SIZE;\ type VTG0_ENABLE;\ @@ -346,4 +350,25 @@ struct dcn10_timing_generator { void dcn10_timing_generator_init(struct dcn10_timing_generator *tg); +struct dcn_otg_state { + uint32_t v_blank_start; + uint32_t v_blank_end; + uint32_t v_sync_a_pol; + uint32_t v_total; + uint32_t v_total_max; + uint32_t v_total_min; + uint32_t v_sync_a_start; + uint32_t v_sync_a_end; + uint32_t h_blank_start; + uint32_t h_blank_end; + uint32_t h_sync_a_start; + uint32_t h_sync_a_end; + uint32_t h_sync_a_pol; + uint32_t h_total; + uint32_t underflow_occurred_status; +}; + +void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, + struct dcn_otg_state *s); + #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ |