diff options
| author | Yue Hin Lau <Yuehin.Lau@amd.com> | 2017-09-14 11:27:34 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-10-21 16:41:38 -0400 |
| commit | d53d7866a795410f7b6a16b1ef0b37825edc794e (patch) | |
| tree | b79feb76a1c35cf96fe8a1af079db5a8610be59d /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | |
| parent | 68d77dd8214e5186d535ec7af29722aaad621824 (diff) | |
drm/amd/display: removing remaining register definitions work around
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 69da293e9b4a..0826d73b9809 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -71,11 +71,7 @@ SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ SRI(OPPBUF_CONTROL, OPPBUF, inst),\ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ - SRI(CONTROL, VTG, inst),\ - SR(D1VGA_CONTROL),\ - SR(D2VGA_CONTROL),\ - SR(D3VGA_CONTROL),\ - SR(D4VGA_CONTROL) + SRI(CONTROL, VTG, inst) #define TG_COMMON_REG_LIST_DCN1_0(inst) \ TG_COMMON_REG_LIST_DCN(inst),\ @@ -128,11 +124,6 @@ struct dcn_tg_registers { uint32_t OPPBUF_CONTROL; uint32_t OPPBUF_3D_PARAMETERS_0; uint32_t CONTROL; - /*todo: move VGA to HWSS */ - uint32_t D1VGA_CONTROL; - uint32_t D2VGA_CONTROL; - uint32_t D3VGA_CONTROL; - uint32_t D4VGA_CONTROL; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ |