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authorAlvin Lee <alvin.lee2@amd.com>2020-09-25 12:24:48 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-10-05 15:17:20 -0400
commit480c5b8ff8757405e07ba938f5c565ecdf38d981 (patch)
treec1233713ff3333ecc6df79c8023e3a7237913d3e /drivers/gpu/drm/amd/display/dc/dcn10
parentb98ab70e748e54b6b53abc2a20380ceb01e421fc (diff)
drm/amd/display: Program meta addresses correctly
[Why] When forcing 3D mode in DAL, we set the right address to be the same as the left address. We need to do the same for the meta addresses. [How] Program right meta to be same as left meta. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 86a0d46ff2e4..9528e3a46b28 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1535,6 +1535,8 @@ static bool patch_address_for_sbs_tb_stereo(
plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
plane_state->address.grph_stereo.right_addr =
plane_state->address.grph_stereo.left_addr;
+ plane_state->address.grph_stereo.right_meta_addr =
+ plane_state->address.grph_stereo.left_meta_addr;
}
}
return false;